1. Field of the Invention
This invention relates to memory interfaces for serial memory, particularly serial EEPROM, in system bus devices, and to methods for avoiding unintended changes to critical information stored in such memories.
2. Description of Related Art
Many integrated circuits (ICs) are configurable for a variety of different applications and require configuration data to set operating parameters. Often, when using a configurable IC, a manufacture connects the IC to a non-volatile memory such as ROM, PROM, EPROM, EEPROM, or flash memory that contains the necessary configuration data. Using an electrically erasable/programmable memory has advantages including the ease with which the memory can be programmed with configuration data during circuit manufacture, the ability to change configuration data without changing components, and the flexibility of being able to store and alter non-critical data in the same memory containing the configuration data. However, a concern when permitting writes to a memory that stores configuration data is the possibility of mistakenly corrupting critical information and making a circuit inoperable. Accordingly, methods and circuits are sought that make unintentional changes to critical data difficult or unlikely but that permit writing to a configuration ROM for changing critical and non-critical data when necessary.
An SEEPROM (serial electrically erasable programmable read only memory) offers a low cost and small foot print memory for critical and non-critical information. A disadvantage of a serial memory such as a SEEPROM is that the serial data stream for reads and writes results in relatively long access times. However, if the stored data is infrequently accessed, the long access times are not a great concern. Another disadvantage is the need to monitor or control each separate bit during an access of a serial memory.
One type interface for reading or writing to an SEEPROM requires software control of accesses to the SEEPROM. For example, computer systems are known which include a host computer and a system bus device such as a PCI card where the system bus device includes to an SEEPROM and the host computer executes a driver which controls and operates the bus device. To access the SEEPROM, the driver controls every aspect of the access, from writing addresses and opcodes to the SEEPROM to asserting clock signals with the appropriate timing and retrieving or sending each bit of data. After the driver initiates an access of the SEEPROM, the driver typically must poll the status of each bit being transferred (read or written) and provide for bit-by-bit transmission of data to or from the SEEPROM. This can be a slow process because SEEPROMs are slow devices, especially for write operations. Accordingly, methods and circuits are desired for reducing the software overhead required for access of an SEEPROM in a bus device.